The metal interconnect of integrated circuits has conventionally been realized by blanket depositing a layer of metal on a substantially planar insulating surface. Portions of the metal layer are subsequently removed in an etching step to form the resulting metal conductors. Copper is preferred due to lower resistivity and better electromigration resistance. Unfortunately, copper is difficult to etch in such a process. Conventional integrated circuits have therefore generally employed a more resistive metal, aluminum, for the metal interconnect.
More recently, a xe2x80x9cdamascenexe2x80x9d process has been developed whereby copper can be used as the interconnected metal. Rather than blanket depositing the interconnect metal on a substantially planar insulating substrate and then etching away parts of the metal layer to leave the conductors, trenches are formed in an insulating material. A layer of interconnect metal is then blanket deposited over the entire surface of the insulating substrate such that the trenches are filled. Chemical mechanical polishing is then used to planarize the integrated circuit surface and thereby polish away all the metal that is not in the trenches. The result is metal conductors disposed in trenches. The term xe2x80x9cdamascenexe2x80x9d derives from the name of the city Damascus. In antiquity, art objects were allegedly decorated in Damascus in similar fashion by embedding precious metals into grooves in their surfaces.
FIGS. 1 and 2 (Prior Art) are cross-sectional diagrams of a damascene antifuse structure from U.S. Pat. No. 5,602,053. Damascene conductor 50 can be permanently coupled to damascene conductor 130 by programming antifuse stack 42-45. Layers 43 and 45 in antifuse stack 42-45 are amorphous silicon, while layers 42 and 44 are silicon nitride. The antifuse stack 42-45 overhangs the underlying damascene conductor 130 by a small amount. A neighboring damascene conductor 61, shown in FIG. 2, has no overlying antifuse but rather has a capping diffusion barrier layer 60 that acts to prevent copper from diffusing up into the insulating material 41 from damascene conductor 61. In U.S. Pat. No. 5,602,053, the conductors 50 and 130 are called xe2x80x9cdual damascenexe2x80x9d conductors because they each include a narrow vertically extending neck or conductive plug portion as well as an overlying and wider horizontally extending conductor portion.
As shown in FIGS. 1 and 2, antifuse stack 42-45 is wider than the underlying damascene conductor 130, which is necessary to prevent copper from diffusing into insulating material 41 and then into the sidewalls of antifuse stack 42-45. Unfortunately, the increased width of antifuse stack 42-45 causes increased leakage and higher capacitance.
Conventional dual damascene technology includes barriers that prevent copper from diffusing into the interlayer dielectric. As shown in FIGS. 1 and 2, antifuse stack 42-45 itself is used as a barrier to prevent diffusion of copper from conductor 130 into insulating material 41. However, these barriers do not prevent impurities from the interlayer dielectric from diffusing into the sidewalls of antifuse stacks 42-45.
Other metals conventionally used in antifuse technology, such as aluminum, tungsten, titanium tungsten, and titanium nitride, have very little diffusion into the standard interlayer dielectric, such as silicon dioxide or TEOS (tetra-ethyl-ortho-silicate). Moreover, TEOS is free of contaminants that could diffuse into the antifuse and degrade performance. Conventionally, antifuses are protected from contaminants with the use of TEOS as an interlayer dielectric. Thus, in conventional antifuse technology there is no need for a barrier to prevent diffusion from the metals into the interlayer dielectric or to prevent diffusion of contaminants from the interlayer dielectric into the antifuse.
However, standard antifuse technology using aluminum type conductors is moving toward lower dielectric constant (xe2x80x9clow-kxe2x80x9d) insulators between metal lines and also between metal layers. A xe2x80x9clow-kxe2x80x9d (low permitivity) material is a class of materials that have dielectric constants of less than 4.0 and preferably equal to or less than 3.5. xe2x80x9cLow-kxe2x80x9d materials, for example, may be fluorine and/or chlorine containing polymers. These materials may have their own contaminants such as mobile potassium and sodium ions. Further, xe2x80x9clow-kxe2x80x9d materials may be a weak barrier to contaminant diffusion.
Ultimately, both these directions are expected to be unified with the use of copper as the interconnect metal and a xe2x80x9clow-kxe2x80x9d dielectric between metal lines and/or layers.
Contaminants, such as copper or impurities, that pass into the antifuse may deleteriously affect antifuse electrical characteristics and/or reliability. Thus, an improved antifuse structure is desired that prevents diffusion of contaminants into the antifuse in both standard metal antifuse architecture as well as in damascene antifuse structures. It is desired to inhibit contaminants (for example, copper) from a damascene conductor from diffusing into the interlayer dielectric and then into the sidewalls of the programmable material in the antifuses. It is also desired to inhibit impurities (for example, fluorine, chlorine, potassium, and sodium ions) that may be present in the interlayer dielectric from diffusing into the sidewalls of the programmable material in the antifuses.
An antifuse structure with an exposed amorphous silicon sidewall includes a diffusion barrier layer, such as silicon nitride or silicon oxynitride, that is deposited on the antifuse sidewall to prevent impurities from diffusing into the antifuse programmable material.
In an embodiment of an antifuse structure using damascene conductors, an antifuse stack is disposed on an upper surface of a damascene conductor containing copper. An insulating diffusion barrier layer covers an upper surface of the damascene conductor that is not covered by the antifuse stack. This insulating diffusion barrier layer inhibits copper from diffusing up into an interlayer dielectric and then laterally into the sidewalls of the antifuse stack. The diffusion barrier layer also covers the sidewalls of the antifuse stack to inhibit contaminants, for example, copper and/or fluorine, chlorine, potassium, sodium ions or the like, from diffusing laterally into the sidewalls of the antifuse stack from the interlayer dielectric. Copper diffuses less readily in the insulating diffusion barrier layer than it does in the interlayer dielectric.
Use of the insulating diffusion barrier layer allows the width of the antifuse stack to be smaller than the underlying damascene trench, which leads to increased packing density and also lower capacitance and leakage.
In an embodiment of an antifuse structure using standard aluminum conductors, an antifuse stack is disposed on an upper surface of a first conductor. Similar to the damascene antifuse structure, an insulating diffusion barrier layer covers a portion of the upper surface of the first conductor not covered by the antifuse stack, and covers the sidewalls of the antifuse stack. The insulating diffusion barrier layer inhibits contaminants from the interlayer dielectric from diffusing into the sidewall of the antifuse stack, which is particularly advantageous where the interlayer dielectric is a xe2x80x9clow-kxe2x80x9d dielectric and/or contains fluorine, chlorine, or other contaminants, such as mobile potassium and/or sodium ions. The insulating diffusion barrier layer may also cover a top surface of the antifuse stack. The antifuse stack is in electrical contact with a second conductor by a conductor plug that extends through the insulating diffusion barrier.
Another embodiment of an antifuse structure with aluminum conductors uses a conductive plug to place the first conductor in electrical contact with the antifuse stack. The antifuse stack is disposed between the plug and the bottom surface of a second conductor. An insulating diffusion barrier layer covers the sidewalls of the antifuse stack and may extend over the top surface of the second conductor. In another embodiment, the insulating diffusion barrier layer covers the top and sidewalls of the antifuse stack. The second conductor is in electrical contact with the antifuse stack through a via in the insulating diffusion barrier. The insulating diffusion barrier layer again inhibits contaminants from an interlayer dielectric and/or passivation layer from diffusing into the sidewall of the antifuse.
This summary does not purport to define the invention. The invention is defined by the claims.